1. Field of the Invention
The present invention relates generally to a PLL (Phase-Locked Loop) circuit, more particularly, to an automatic bias adjustment circuit adjusting a bias current provided to a CCO (Current Controlled Oscillator).
2. Description of the Related Art
FIG. 8 shows a schematic configuration of a prior art voltage controlled oscillator (VCO) 10 for use in a PLL circuit.
In the VCO 10, a control voltage VC is converted into a current IE by a V/I converter circuit 11, and the current IE is added to a bias current IB by an adder 12 to make a control current IC, which is provided to a current-controlled oscillator (CCO) 13. The CCO 13 outputs an oscillation clock OCLK with a frequency FO according to the value of the control current IC.
FIG. 9(A) shows characteristics of the oscillation frequency FO versus the control voltage VC of the VCO 10 when the bias current IB=0.
The characteristics vary largely with variations in fabrication process conditions, that is, variations in threshold voltage, gate length and gate insulating film thickness of FETs which are constituents of the VCO 10. A characteristic curve TYP in the figure is of a typical case, while other characteristic curves POW and SPW are of cases where the oscillation frequency FO are equal to the maximum and the minimum, respectively, for each control voltage VC because of variations in the fabrication process conditions.
In the PLL circuit, the control voltage VC is an output of a loop filter. The range of variable frequencies VL to VH of the output is usually determined by a power supply voltage and the threshold of FETs. In a case where a frequency Fm is equal to a reference clock frequency when the control voltage VC is equal to the middle value Vm between VL and VH, the range of a frequency of the VCO 10 in which the frequency can vary in the PLL circuit is maximized. Even if the VCO 10 is designed in this way, the VCO 10 is apt to become out of lock due to noise or a variation in clock frequency since the range of the frequency in which it can vary is narrow in a case where the frequency characteristic thereof is of POW according to variations in the fabrication process conditions. While in a case where the frequency characteristic thereof is of SPW, the VCO 10 cannot achieve in lock.
However, even in a case where the frequency characteristic thereof is of POW, if POW is translated in the positive direction along the VC axis to a position as shown in FIG. 9(B), the range of variable frequencies becomes wider to prevent the VCO 10 from being out of lock. The translation corresponds to adjustment of the value of the bias current IB so as to hold FO=Fm when VC=Vm in FIG. 8.
In the PLL circuit, if noise is superimposed on the control voltage VC, jitter arises in the waveform of the oscillation clock OCLK. It is possible to reduce the jitter by decreasing the ratio of an increment of the oscillation frequency FO to an increment of the control voltage VC (a VCO gain), that is, by decreasing the slope of the characteristic curve of the VCO 10.
On the other hand, the characteristics of the VCO 10 are also dependent on temperature as shown in FIG. 10(A). Characteristic curves in the figure show ones in cases where temperatures are T1, T2 and T3 wherein a relation T1 less than T2 less than T3 is satisfied. FIG. 10(B) shows a relationship between temperature T and the oscillation frequency FO under the condition that the control voltage VC is at a constant value.
If the VCO gain is small as shown in FIG. 10(A), the range of variable frequencies and a margin in the PLL circuit are narrow; therefore, a more correct adjustment of the bias current IB is required in order to prevent out of lock which is caused by variations in temperature and noise.
In JP 10-84278 A, a PLL circuit employing a replica of a CCO is used as an automatic bias adjustment circuit, and the output of a V/I converter circuit in a VCO is used as a bias current IB to the PLL circuit, which is an adjustment object, to deal with variations in process conditions and temperature.
However, when the VCO gain of the PLL circuit to be adjusted is reduced in order to restrict jitter to a low, the VCO gain of the bias adjustment circuit is also reduced; therefore, out of lock is easy to arise in the bias adjustment circuit, thereby disabling a proper bias current IB to be generated.
Meanwhile in JP 11-177416 A, in order to cope with variations in process conditions and temperature, the output of a loop filter is converted into a current by a D/A converter circuit to use the current as a bias current IB. However, since the bias current IB is proportional to the control voltage VC in this case, the control current of the CCO is also proportional to the control voltage VC; therefore the control current IC cannot be set to a value at the middle point of its range against variations in process conditions and temperature.
Furthermore in JP 10-70458 A, in order to cope with variations in process conditions and temperature, the output voltage of a loop filter is compared with a reference voltage having a temperature coefficient of almost zero, the count value of a counter is changed in accordance with the result of the comparison, and a bias switch is controlled by the count value to determine the state of a bias generator.
However, there is no description about how to change the count value, what the reference voltage is, how relationship between the input and output of the bias generator goes, how the output current range of the bias generator is limited by the bias switch, which makes the contents of the bias adjustment left unclear. Moreover, since the bias generator is always under digital control in order to deal with variation in temperature, since the value of the control current IC has a step change at each time of changing-over of the switch to produce jitter even on the assumption that the bias adjustment is enabled.
Furthermore, since in any of the above-published documents, the digital adjustment circuit is always in operation in order to deal with variation in temperature, power consumption increases.
Accordingly, it is an object of the present invention to provide an automatic bias adjustment circuit capable of giving a more proper bias current to a PLL circuit against variations in process conditions and temperature.
An automatic bias adjustment circuit according to present invention is for use in a PLL circuit. The PLL circuit is provided with voltage-controlled oscillator comprising: a voltage to current converter circuit converting a control voltage VC to a current IE; and a current-controlled oscillator receiving a control current IC which is obtained by adding a bias current IB to the converted current IE.
In one aspect of the automatic bias adjustment circuit according to present invention, the bias current IB is the sum of a first bias current adjusted for dealing with process variations and a second bias current for dealing with temperature variation. These first and second biases current are generated by a bias adjustment circuit and a bias current generating circuit, respectively.
The bias adjustment circuit adjusts the first bias current in response to an adjustment start signal such that the control voltage converges to a reference voltage, and ceases the adjustment when the convergence has been achieved.
The reference voltage is determined to be an almost middle point in the range of the variable control voltage.
The bias current generating circuit provides the second bias current having such a temperature characteristic that the control voltage is prevented from shifting from the reference voltage due to temperature variation.
Since the adjustment by the bias adjustment circuit is not performed after the first bias current having been adjusted such that the control voltage converges to the reference voltage, even if the characteristics of the voltage-controlled oscillator changes due to variation in temperature, the value of the first bias current does not rapidly change, thereby ensuring a stable operation of the PLL circuit.
After the adjustment, since the shift of the control voltage from the reference voltage due to variation in temperature is corrected by the bias current generating circuit, the control voltage is maintained at an almost middle point in the range of the variable control voltage. Thereby, the range of variable oscillation frequencies with maintaining in lock becomes almost the maximum independently of variation in temperature, and therefore even if the VCO gain is reduced in design in order to minimize jitter due to noise, it is possible to prevent out of lock from occurring.
In a case where the bias current generating circuit is constituted of a bias voltage generating circuit and a voltage to current converter circuit converting a generated bias voltage to a current which is the second bias current, the bias voltage generating circuit generates the bias voltage having a temperature characteristic which is reverse to that of the control voltage under the condition that the frequency of the oscillation signal is fixed.
Other aspects, objects, and the advantages of the present invention will become apparent from the following detailed description taken in connection with the accompanying drawings.